Use of on-chip inductance structures (e.g., T-coils and inductors) in VLSI design is becoming more prevalent as design frequencies increase. These structures are metal-only devices within a chip where “coils” of metal are created on wiring layers in an attempt to create inductance. This inductance is useful in high speed applications that are performance-limited due to capacitive loading. Due to its nature, these structures have a low inductance per unit area; a recent design demonstrated ˜1.5 nH per 2185 um2 of area. One can/may increase the inductance per unit area of silicon Back End Of Line (BEOL) inductance structures such as T-coils and inductors.
The spiral of prior art does not allow for the use of external ferrites, and in the one instance does not have each coil of the spiral an equal distance from the core. Thus the flux linking thru the core is not optimized. Further, the prior art fundamentally provides for flux linkage thru horizontal structures, i.e., not utilizing a more vertical structure to reduce surface area for a given inductance.
Another prior art teaches a planar inductor with orthogonal windings, intermingled and encased in magnetic materials. It includes teaching regarding vapor deposition of materials wherein, the core is formed primarily thru flat plates, and intermingled strips of “magnetic” materials.
Another prior art teaches a planar spiral inductor around a core formed by photoresist etching and a horizontal spiral around a patterned core.